
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   01:39:45 02/02/2011
-- Design Name:   RAM
-- Module Name:   E:/test_ram/tb_ram.vhd
-- Project Name:  test_ram
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RAM
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_ram_vhd IS
END tb_ram_vhd;

ARCHITECTURE behavior OF tb_ram_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT RAM
	PORT(
		Reset : IN std_logic;
		Clk : IN std_logic;
		Address : IN std_logic_vector(7 downto 0);
		CS : IN std_logic;
		write_en : IN std_logic;
		OE : IN std_logic;    
		Databus : INOUT std_logic_vector(7 downto 0);      
		Switches : OUT std_logic_vector(7 downto 0);
		Temp_L : OUT std_logic_vector(6 downto 0);
		Temp_H : OUT std_logic_vector(6 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL Reset :  std_logic := '0';
	SIGNAL Clk :  std_logic := '0';
	SIGNAL CS :  std_logic := '0';
	SIGNAL write_en :  std_logic := '0';
	SIGNAL OE :  std_logic := '0';
	SIGNAL Address :  std_logic_vector(7 downto 0) := (others=>'0');

	--BiDirs
	SIGNAL Databus :  std_logic_vector(7 downto 0);

	--Outputs
	SIGNAL Switches :  std_logic_vector(7 downto 0);
	SIGNAL Temp_L :  std_logic_vector(6 downto 0);
	SIGNAL Temp_H :  std_logic_vector(6 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: RAM PORT MAP(
		Reset => Reset,
		Clk => Clk,
		Databus => Databus,
		Address => Address,
		CS => CS,
		write_en => write_en,
		OE => OE,
		Switches => Switches,
		Temp_L => Temp_L,
		Temp_H => Temp_H
	);
clking: PROCESS
	BEGIN
		CLK <= '1', '0' after 25 ns;
		wait for 50 ns;
   END PROCESS;
	
	tb : PROCESS
	BEGIN

		CS         <= '0';
      Reset      <= '0', '1' after 10 ns;
      Write_en   <= '1', '0' after 2200 ns;
      OE         <= '0', '1' after 2200 ns;
      ADDRESS    	 <= X"00", 
                      X"01" after 100 ns, 
                      X"02"after 200 ns, 
							 
                      X"10" after 300 ns, 
                      X"11"after 400 ns,
                      X"12" after 500 ns, 
                      X"13" after 600 ns, 
                      X"14" after 700 ns, 
                      X"16" after 800 ns,
                      X"17" after 900 ns, 
							 
                      X"20" after 1000 ns, 
                      X"21" after 1100 ns, 
                      X"22" after 1200 ns,
                      X"23" after 1300 ns, 
                      X"24" after 1400 ns, 
                      X"25" after 1500 ns, 
                      X"26" after 1600 ns,
                      X"27" after 1700 ns, 
                      X"28"after 1800 ns, 
                      X"28" after 1900 ns, 
                      X"29"after 2000 ns,
							 
                      X"31" after 2100 ns,
                      
							 X"00" after 2200 ns,
                      X"01" after 2300 ns, 
                      X"02"after 2400 ns, 
							 
                      X"10" after 2500 ns, 
                      X"11"after 2600 ns,
                      X"12" after 2700 ns, 
                      X"13" after 2800 ns, 
                      X"14" after 2900 ns, 
                      X"16" after 3000 ns,
                      X"17" after 3100 ns, 
                      X"20" after 3200 ns, 
                      X"21" after 3300 ns, 
                      X"22" after 3400 ns,
                      X"23" after 3500 ns, 
                      X"24" after 3600 ns, 
                      X"25" after 3700 ns, 
                      X"26" after 3800 ns,
                      X"27" after 3900 ns, 
                      X"28"after 4000 ns, 
                      X"28" after 4100 ns, 
                      X"29"after 4200 ns,
							 
                      X"31" after 4300 ns;
                      
        Databus 	<= "00000000", 
                     "00000001" after 100 ns, --1
                     "00000010" after 200 ns, --2
                     "00000011" after 300 ns, --3
                     "00000100" after 400 ns,--4
                     "00000101" after 500 ns, --5
                     "00000110" after 600 ns, --6
                     "00000111" after 700 ns, --7
                     "00001000" after 800 ns,--8
							
                     "00000001" after 900 ns, --1
                     "00001010" after 1000 ns, --10
                     "00001011" after 1100 ns, --11
                     "00001100" after 1200 ns,--12
                     "00001101" after 1300 ns, --13
                     "00001110" after 1400 ns, --14
                     "00001111" after 1500 ns, --15
                     "00010000" after 1600 ns,--16
                     "00010001" after 1700 ns, --17
                     "00010010" after 1800 ns, --18
                     "00010011" after 1900 ns, --19
                     "00010100" after 2000 ns,--20
                     "00010101" after 2100 ns,--21
                     (others => 'Z') after 2200 ns;
               wait for 5000 ns;
			END PROCESS;

END;
